SoC's are usually designed using a combination of third party, internal, and foundry Intellectual Property (IP). Typically these ICs are built upon a bulk CMOS process, potentially resulting in non-optimal process characteristics for circuitry other than standard digital logic. Achieving target specifications for these blocks is becoming increasingly difficult as semiconductor geometries approach single digits in nm.
A better approach is to select the optimum technology for each functional block of the IC and stitch these Heterogeneous chiplets together into a System of Chiplets.
There are some challenges with this approach however. Typically, interconnect density is limited by the pick and place accuracy of the equipment reconstituting the SoC from its component chiplets. For example, with +/- 5 micron placement accuracy, connections can only be made every 10 microns.
With its patented technology, CrossFire has broken this barrier. Interconnect density tighter than typically implementable is now possible! This capability is a tremendous advantage for high pin count interfaces such as High Bandwidth Memory (HBM)
CrossFire categorizes its semiconductor interconnect into two classes:
CrossFire Connected refers to the process of connecting ICs or chiplets that utilize standard Input Output (IO) circuitry. In this case, the CrossFire process simply interconnects standard ICs.
Typical semiconductor IOs include ESD protection and are designed to drive high capacitance package interconnect traces. When connecting chiplets however, this circuitry is not optimized for the use case and winds up using more power and taking up more area than required.
The solution is CrossFire Architected interconnect. By using its unique approach, CrossFire can interconnect two standard devices. If the chiplets actually integrate the solution into their IOs, then even greater density is available.
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