Revolutionizing Chiplet Connectivity and Integration
Moore’s Law (the doubling of transistor density on a chip every 18 months) has driven the semiconductor industry for decades, but the era of scaling geometries downward every two years is coming to an end due to physics and economics. The industry solution to this problem is “Chiplets” - the partioning a large monolithic die into individual Heterogeneous die that are then integrated together to form an SoC.
Nothing is ever free in semiconductors though, especially with Chiplets. Some of the challenges that “Chipletization” faces are:
With Chiplets, a “Die to Die” PHY Interface is required for chiplet to chiplet connectivity, which requires additional die area and increases system power.
The integration of Chiplets is almost always done with a Silicon Interposer, increasing design complexity, cost, power, and time to market.
CrossFire solves these Chiplet connectivity and integration challenges, eliminating the need for advanced packaging to create Chiplet based designs. CrossFire’s Patented and Proprietary Die to Die Interface requires minimal additional die area compared to current “SerDes like” solutions. Interposers are not required with CrossFire’s Patented and Proprietary Chiplet integration process, eliminating interposer cost, reducing development time, and lowering Die to Die interconnect power.
With CrossFire, design engineers are able to move from just scaling chip features to scaling system functionality.
