Expanding the
Open Chiplet Economy
Up to 50% reduction in Chiplet Die Area
50x smaller, 10x less energy/bit, 10x lower upfront cost
Chiplet integration without Interposers
Up to 50% reduction in Chiplet Die Area
50x smaller, 10x less energy/bit, 10x lower upfront cost
Chiplet integration without Interposers
| Bridgelet | Direct Chiplet Interface (DCI) | |||||
|---|---|---|---|---|---|---|
| Features | Benefits | Features | Benefits | Disaggregates system I/O from memory functions | Allows chiplet reuse within or across product families | Ultra Short Reach (<500µ) | Lower power and area; Higher performance |
| Die scale interconnect (sub-micron) | Higher density and performance; Lower power | Protocol Agnostic | One PHY for multiple protocols | |||
| Enables “Beyond the Reticle” constraint | Extend SoC designs | Die Scale Interconnect (sub-micron) | Higher density and performance; Lower power | |||
A Bridgelet is a Chiplet that enables customers to reuse existing IP with two different Die to Die interfaces as well as reduce interface die area by 50x. This can dramatically reduce SoC development and manufacturing costs while also accelerating time to market. A Bridgelet can also contain key system functionality such as UCIe or LPDDR5x interfaces connected to the main xPU Chiplet by an on-chip interface such as AMBA-AXI5 or AMBA-CHI that uses CrossFire’s Direct Chiplet Interface (DCI).
Requiring less than 0.1mm**2 of die area to extend a 128-bit AMBA-AXI5 on-chip fabric between Chiplets, DCI minimizes both System and IC development costs and schedules. Requiring less than 100 Femto Joule per bit of transfer energy and adding practically zero latency, DCI is the ultimate Die to Die Interface solution.
CrossFire has developed an approach to Chiplet Integration that does not require an Interposer or expensive ultra-fine pitch package laminate. The output of CrossFire’s OmniLithic Chiplet Integration Process creates a DIE – not a SiP. Chiplets integrated into an OmniDie are compatible with standard packaging, require no interposer, and support Wafer Scale Integration.