Xilinx MPSoC based System in Package (SiP) Devices
The CrossFire System in Package (SiP) Platform is architected as a “concept to production” answer to the challenges of engineering, prototyping and releasing to production a miniaturized System in Package (SiP) devices based on the Xilinx MPSoC family of field programmable gate arrays (FPGAs). Similar in footprint to standard Xilinx FPGAs, CrossFire’s MPSoC based SiP devices fit within standard FPGA footprints while integrating DDR4 and Serial Boot ROM resources. .
Recognizing that additional functionality, size, or pinout may be required to meet system requirements, customized implementations are supported to efficiently enable engineering teams to meet their system requirements.
| Requirement | CrossFire's Solution |
|---|---|
| A customizable and readily available hardware and software “evaluation platform” that satisfies the base requirements of a particular use case or market and facilitates a proof of concept (PoC) prototype. | Customers can begin their “proof of concept” (PoC) development utilizing the currently existing ecosystem of Xilinx evaluation boards. CrossFire recommends either the Xilinx “ZCU” family of evaluation kits or the “UltraZed” family of MPSoC-based carrier cards as starting points. |
| A seamless path from PoC to engineering prototype, pre-production, and then production-qualified devices. | Once the proof of concept is finalized, it is on to the engineering prototype. With CrossFire, the typical path is to start with one of our existing modules. Some applications will be able to utilize a module as is, while others will need tweaking to meet the PoC requirements. This process typically takes 3 – 12 months, depending on the degree of customization required. |
| A comprehensive ecosystem (including software, prototyping resources, intellectual property, validation, and certification) to support the device development throughout its lifecycle. | Through its partnership with Xilinx, CrossFire customers have access to their extensive design ecosystem which enables the use of complex FPGAs in various applications. CrossFire’s modules are compatible with Xilinx’s Vivado platform, providing a seamless transition from proof of concept to volume production |
| Xilinx MPSoC |
Footprint (mm x mm) |
PS DRAM (DDR4) |
PL DRAM (DDR4) |
Boot Flash (Quad SPI) |
|---|---|---|---|---|
| ZU9-EG | 31 x31 | 2GB, 4GB | Optional | 512Mb |
| ZU7-EV | 31 x 31 | 2GB, 4GB | 2GB, 4GB | 512Mb |
| ZU5-EV | 31 x 31 | 2GB, 4GB | 2GB, 4GB | 512Mb |
| ZU3-EG | 19 x 19 23 x 23 | 2GB, 4GB 2GB, 4GB | None Optional | 512Mb |
| ZU28 | TBD | TBD | TBD | TBD |
Module Design (Not to scale)
Customized System in Package Devices and Application-Specific Standard Products (ASSPs)
As design engineers attempt to cover as many use cases as possible within the definition of a standard product, the tradeoffs can sometimes turn “one size fits all” into “one size fits none.” As an alternative, CrossFire can easily customize a System in Package Device or develop an ASSP based on Chipletsto better fit a given use case. For example, a SiP footprint could be changed to better fit system requirements. Functionality can be added or subtracted (doubling or removing DRAM, for example); resources can be substituted (replace DRAM with Flash), or virtually any design modification required.
Full Custom Solutions
To design a fully optimized system often requires starting with a blank sheet of paper, and CrossFire’s technology excels in this space. On average, CrossFire’s design platform can deliver most of the functionality of a System on Chip (SoC) with our Heterogeneous System on Chip (HSoC) offering – in less than 25% of the time with significantly lower cost. This HSoC can then be combined with standard ASSP and FPGA die into a die-based module to yield the maximum benefit in performance, power, size, and weight for the particular application. Full custom designs can even become the basis for a “company specific standard product,” which can then be tuned for different applications.
CROSSFIRE CHIPLET SYSTEM
The typical design process for System-on-Chip (SoC) designs involve a combination of internal, third party, and foundry intellectual property (IP) blocks. Often these ICs are built on a bulk CMOS process, which may result in non-optimal characteristics for circuitry other than standard digital logic. Achieving target specifications for these blocks is becoming increasingly difficult as semiconductor geometries approach single digits in nanometers.
Typical 4G SoC
A better approach would select the optimum technology for each functional block of the IC and stitch these heterogeneous chiplets together into a “System of Chiplets.” However, the design challenge using this approach is that conventional interconnect density is limited by the accuracy of the pick-and-place equipment used to reconstitute the SoC from its component chiplets – typically about ±5 microns. Thus, connections can only be made in 10-micron increments.
Crossfire’s patented technology has broken this barrier with Interconnect densities tighter than previously implementable, delivering a significant advantage for design engineers using high pin count interfaces, such as high bandwidth memory (HBM).
CrossFire’s semiconductor interconnect is characterized in two classes:
CrossFire Connected
CrossFire Connected refers to the process of connecting ICs or chiplets using standard Input/Output (I/O) circuitry. In this case, the CrossFire process simply interconnects standard ICs to achieve higher density interconnections.
CrossFire Architected
Conventional semiconductor I/Os include ESD protection and are designed to drive high capacitance package interconnect traces. However, when connecting chiplets, this type of circuitry is not optimized for the use case, resulting in higher power consumption and taking up more area than required.
CrossFire Architected interconnect uses a unique approach to interconnect two standard devices with higher density. By integrating the desired functionality into the chiplet I/Os, even greater density is available.