Die to Die (D2D) iP

CrossFire’s D2D solution - Direct Chiplet Interface™ (DCI™) will be offered in two implementations:

  • Intellectual Property (IP) Cores that can be integrated into a customer’s Chiplet Design.

  • Instantiated in a “Bridgelet™” die that can be used to bridge between different D2D interfaces.

bridglets 

Multiple standard D2D interface implementations are present in the market, with additional implementations in development. Add the proprietary implementations already in use, and the issue of using chiplets that implement different D2D interfaces in the same design surfaces. CrossFire’s solution to this issue is a small Chiplet that we call a Bridgelet™. For example, a Bridgelet could interface between two Chiplets that use different D2D interfaces.

CrossFire’s first Bridgelet will be a DCI to UCIe device. This device will enable CrossFire customers that have integrated DCI connectivity into their Chiplets to connect to Chiplets equipped with the standard high power, low density UCIe interface.

DCI™ Intellectual property

An optimum deployment of DCI in a Chipletized system would implement full DCI interfaces on all Chiplets. To this end, CrossFire will be offering DCI in most flavors of TSMC silicon at 7nm and below. Other manufacturers and technologies are also under consideration, please email us at sales@crossfire-tech.com for more information.

If necessary, DCI can also be utilized in a multi-Chiplet system with limited DCI connectivity by working directly with CrossFire to optimize the other Chiplets via CrossFire’s proprietary post fab die processing capabilities to mostly achieve the lower power and improved performance characteristics of fully DCI connected systems

CrossFire will also consider working with a customer / standards body for a custom implementations of DCI - for example:

  • To reduce the power and die area of the proprietary interface of an Integrated Device Manufacturer (IDM) or Fabless Semiconductor Company.

  • To enable the use of standard “on-chip” fabrid interfaces such as CHI or VCIX in Chipletized environments.

  • Improving the performance metrics of a standard off-chip interface such as CXL in a Chipletized environment